SST49LF080A-33-4C-WHE-T【PDF 5/50 页】IC FLASH SER LPC 8MBIT 32TSOP

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8 Mbit LPC Flash

A Microchip Technology Company

SST49LF080A

Data Sheet

Table 1: Pin Description

Interface

Symbol

Pin Name

Type 1

PP LPC Functions

A 10 -A 0

Address

I

X

Inputs for low-order addresses during Read and Write operations.

Addresses are internally latched during a Write cycle. For the pro-

gramming interface, these addresses are latched by R/C# and share

the same pins as the high-order address inputs.

DQ 7 -DQ 0 Data

I/O

X To output data during Read cycles and receive input data during

Write cycles. Data is internally latched during a Write cycle. The out-

puts are in tri-state when OE# is high.

OE#

WE#

MODE

Output Enable

Write Enable

Interface

Mode Select

I

I

I

X To gate the data output buffers.

X To control the Write operations.

X X This pin determines which interface is operational. When held high,

programmer mode is enabled and when held low, LPC mode is

enabled. This pin must be setup at power-up or before return from

reset and not change during device operation. This pin must be held

high (V IH ) for PP mode and low (V IL ) for LPC mode.

INIT#

Initialize

I

X This is the second reset pin for in-system use. This pin is inter-

nally combined with the RST# pin; If this pin or RST# pin is driven

low, identical operation is exhibited.

ID[3:0]

Identification

Inputs

I

X These four pins are part of the mechanism that allows multiple parts to

be attached to the same bus. The strapping of these pins is used to

identify the component.The boot device must have ID[3:0]=0000 for all

subsequent devices should use sequential up-count strapping. These

pins are internally pulled-down with a resistor between 20-100 K ?

GPI[4:0]

General

Purpose

Inputs

I

X These individual inputs can be used for additional board flexibility. The

state of these pins can be read through LPC registers. These inputs

should be at their desired state before the start of the PCI clock cycle dur-

ing which the read is attempted, and should remain in place until the end

of the Read cycle. Unused GPI pins must not be floated.

TBL#

Top Block

Lock

I

X When low, prevents programming to the boot block sectors at top of

memory. When TBL# is high it disables hardware write protection for

the top block sectors. This pin cannot be left unconnected.

LAD[3:0] Address and

Data

LCLK Clock

LFRAME# Frame

I/O

I

I

X To provide LPC control signals, as well as addresses and Command

Inputs/Outputs data.

X To provide a clock input to the control unit

X To indicate start of a data transfer operation; also used to abort

an LPC cycle in progress.

RST#

Reset

I

X X To reset the operation of the device

WP#

Write Protect

I

X

When low, prevents programming to all but the highest addressable

blocks. When WP# is high it disables hardware write protection for

these blocks. This pin cannot be left unconnected.

R/C#

Row/Column

I

X

Select for the Programming interface, this pin determines whether the address

Select

pins are pointing to the row addresses, or to the column addresses.

RES

Reserved

X

These pins must be left unconnected.

V DD

V SS

Power Supply

Ground

PWR

PWR

X X To provide power supply (3.0-3.6V)

X X Circuit ground (0V reference)

CE#

Chip Enable

I

X

This signal must be asserted to select the device. When CE# is low,

the device is enabled. When CE# is high, the device is placed in low

power standby mode.

NC

No Connection

I

X X

Unconnected pins.

T1.0 25026

1. I=Input, O=Output

?2011 Silicon Storage Technology, Inc.

5

DS25086A

11/11

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